Category : Electrical and electronic equipment & instrumentations > Electrical protection devices, fuses

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TestWay PCB testability analyzer enables earlier measurement and improvement of testability, even during the schematic design stage. Improved testability yields great savings by reducing production test costs and increasing fault coverage.
How it works:
TestWay reads the board level netlist (schematic or layout) and model libraries. It performs a basic topological analysis and symbolic simulation. It then checks each rule, using both topological and accessibility data. TestWay writes to the report file an accurate English language description of any non-conformance. TestWay also writes valuable statistical data to the report file which is useful in fixture design, budgeting and resource allocation.
- TestWay supports 37 CAD importers for both schematic and layout information.
- TestWay requires a model for each device in case there are no testability information included in the schematic description.
- Schematic model translators, BSDL and IBIS compilers.

Built-in and custom rules:
TestWay's rule set is derived from formal standards and includes rules commonly applied in the electronics industry.
- Design rules verify conformance to restrictions imposed by certain technologies (open-collector, open-emitter, HCMOS).
- In-Circuit test rules insure partitioning and initialization pin controllability (SET-RESET, Chip select, Output enable, Test)
- Boundary-Scan test rules check Boundary Scan path integrity (JTAG) and test bus control.
- Customer’s rules meet any specific in-house testability requirements. User may define and integrate new custom rules.

Test Point Savers:
With the dramatic increase in device density on PCB’s, it is very difficult to access each of the nets for test purpose. Balancing different test approaches (AOI, AXI, BST, FCT, FPT, ICT…), TestWay optimizes the number of mandatory test accesses.

Coverage prediction:
TestWay can estimate potential fault coverage based on available physical and virtual test points. This comes, in handy, at the schematic stage or during layout, thereby permitting improved access before the design reaches the test department.
See a test coverage report (PDF file, 54k)

Program set generation:
TestWay generates input files for Boundary-scan and In-Circuit testers including board description and models.

Coverage measurement:
Reading real test programs or coverage reports, TestWay controls real test efficiency against theoretical coverage. It identifies uncovered area and redundancy tests.

Benefits in Concurrent Engineering:
TestWay unlocks the great potential benefits of concurrent engineering.
- Higher test coverage by identifying testability issue while designers are still able to make modifications.
- Higher test coverage by identifying optimal test points and back-annotating them into the schematic.
- Fewer iterations through layout because test points can be assigned prior to layout.
- Lower fixture costs because of fewer test points.
- Faster time to market because many test problems can be resolved at the schematic stage.
- Faster time to market because test programs can be substantially developed prior to layout.

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